Skip to Main content Skip to Navigation
Journal articles

The Design and FPGA-Based Implementation of a Stream Cipher Based on a Secure Chaotic Generator

Abstract : In this study, with an FPGA-board using VHDL, we designed a secure chaos-based stream cipher (SCbSC), and we evaluated its hardware implementation performance in terms of computational complexity and its security. The fundamental element of the system is the proposed secure pseudo-chaotic number generator (SPCNG). The architecture of the proposed SPCNG includes three first-order recursive filters, each containing a discrete chaotic map and a mixing technique using an internal pseudo-random number (PRN). The three discrete chaotic maps, namely, the 3D Chebyshev map (3D Ch), the 1D logistic map (L), and the 1D skew-tent map (S), are weakly coupled by a predefined coupling matrix M. The mixing technique combined with the weak coupling technique of the three chaotic maps allows preserving the system against side-channel attacks (SCAs). The proposed system was implemented on a Xilinx XC7Z020 PYNQ-Z2 FPGA platform. Logic resources, throughput, and cryptanalytic and statistical tests showed a good tradeoff between efficiency and security. Thus, the proposed SCbSC can be used as a secure stream cipher.
Document type :
Journal articles
Complete list of metadata
Contributor : Admin Hal Ur1 Connect in order to contact the contributor
Submitted on : Tuesday, May 25, 2021 - 2:59:11 PM
Last modification on : Saturday, June 5, 2021 - 3:36:27 AM
Long-term archiving on: : Thursday, August 26, 2021 - 8:03:31 PM


Publisher files allowed on an open archive



Fethi Dridi, Safwan El Assad, Wajih El Hadj Youssef, Mohsen Machhout, René Lozi. The Design and FPGA-Based Implementation of a Stream Cipher Based on a Secure Chaotic Generator. Applied Sciences, MDPI, 2021, 11 (2), pp.625. ⟨10.3390/app11020625⟩. ⟨hal-03106699⟩



Record views


Files downloads