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Modeling, Scheduling, Pipelining and Configuration of Synchronous Dataflow Graphs with Throughput Constraints

Abstract : Multi-Processors System-on-Chip (MPSoC) are now embedded in more and more devices, for example, in smart cameras which can run image processing applications in real-time. Designing applications that fully exploit the capacity of an MPSoC is a complex task that requires addressing multiple constraints such as maximum energy consumption to preserve the battery and minimal frame rate to ensure a good video quality. This thesis adopts a global approach to the design problem, from modeling to tuning, thanks to fast analysis and synthesis heuristics. To do so, the designed application is first modeled independently from any MPSoC. The application is later automatically tuned and mapped on a MPSoC thanks to an analysis and synthesis framework. The models used in this thesis derive from the Synchronous DataFlow (SDF) Model of Computation (MoC), while the analysis and synthesis framework is PREESM. In this thesis, three aspects of the design process have been addressed, all at the software level: the modeling of iterative loops, the scheduling of real-time constraints, and the pipelining of tasks. A fourth contribution combines all these aspects: a Design Space Exploration (DSE) algorithm taking into account throughput, latency, and energy constraints. This DSE makes it possible to automatically tune the parameters of an application so that all constraints are met. All the contributions have been implemented and evaluated in the PREESM framework.
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Submitted on : Wednesday, September 8, 2021 - 1:07:10 PM
Last modification on : Friday, September 10, 2021 - 3:34:48 AM


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  • HAL Id : tel-03337988, version 1


Alexandre Honorat. Modeling, Scheduling, Pipelining and Configuration of Synchronous Dataflow Graphs with Throughput Constraints. Signal and Image processing. INSA de Rennes, 2020. English. ⟨NNT : 2020ISAR0010⟩. ⟨tel-03337988⟩



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